Can you please run the same test at let's say 100KHz master CLK from DSP.
To my understanding SUB-20 FIFO module is not fast enough to update next byte to be sent and thus it shifts out byte received before.
The 100 KHz (or less) test will show it for sure.
At less than 100Khz it appears to work correctly. How come in that case a read from the SUB-20 app works at more than 100Khz but a write does not? I am taking from all that the max speed i can use the FIFO at is 100Khz.
Hi,
Let's increase the speed. Please try 250KHz and 400KHz.
Usually in SPI communication there is a byte to byte delay that is used by FIFO to provide next byte.
Our SPI module is bidirectional. It has double buffer in one direction but not in another. This is the reason I think.
